This invention relates generally to computer systems and more specifically to data transfers within computer systems.
As it is known in the art, in order for components comprising a computer system to use data stored in main memory or in other components, there needs to be a communication channel dedicated to inter-component data communication. Such a communication channel is typically comprised of a data bus having a protocol specifying proper use of the data bus.
One such protocol used in the industry is the Direct Memory Access protocol, referred to as DMA. DMA is a method for allowing a component having DMA capabilities to control the reading and writing of data to or from a target device. DMA is a very efficient data transfer methodology because the central processing unit (CPU) does not need to be directly involved in the transaction. Since the CPU does not need to control DMA data transfers, it is free to perform other computing tasks. Therefore, not only does DMA allow for quick data access, it also increases the system's overall performance by allowing the CPU to concurrently perform other necessary computations.
One implementation of DMA is used as part of the Peripheral Component Interconnect (PCI.TM.) data bus standard. The PCI.TM. standard is an overall bus architecture standard which governs the physical features of a bus as well as the structure of data transfers using the bus. The specified data bus structure allows each component connected to the bus to become either a bus master device, which controls transactions on the bus, or a target device which is accessed by a bus master device.
To become a bus master, a device asserts a request signal connected to an arbitration unit referred to as the bus arbiter. Using one of a variety of arbitration schemes, the arbiter grants ownership of the PCI.TM. bus to a bus master device at the appropriate time. Once a device acquires ownership of the bus, it is allowed to initiate a data transfer between itself and a target device, which is typically a shared memory subsystem.
A data transfer, employing the PCI.TM. standard, is initiated when the bus master device places the address of a desired data element and a command onto the address/data bus and asserts a signal referred to as FRAME. The FRAME signal defines the outer timing boundaries of the transfer, i.e. its assertion and deassertion (along with the IRDY and TRDY signals defined below) indicates the beginning and ending of the data transfer. After or coincident with the bus master asserting the FRAME signal, it further asserts an Initiator Ready signal referred to as IRDY. The assertion of this signal indicates that the bus master device is ready to transfer the first data word.
When the target device decodes the address it asserts signal DEVSEL and, when it is ready to transfer or receive data, asserts a target ready signal referred to as TRDY. Data is only transferred when the TRDY and IRDY signals are concurrently asserted. Alternatively it should be noted that when the signal TRDY is de-asserted, this indicates to the bus master device that the target is not ready to be accessed with the next word of data. When the FRAME signal is de-asserted, the bus master terminates the transfer after attempting one further data phase. To terminate the data transfer, the bus master relinquishes control of the PCI.TM. bus to allow another device to become bus master and to initiate its own data transfer cycle. Accordingly, a read or write cycle on the PCI.TM. bus is completely controlled by the bus master device and the target device with no intervention by the central processing unit.
Certain problems can arise when transferring data using a DMA data transfer mechanism over the PCI.TM. bus. As previously mentioned, a data transfer only occurs when both the TRDY and IRDY signals are asserted. If a target device is busy and cannot support a data transfer, it will not assert the TRDY signal. Alternatively, if a target begins a data block transfer but subsequently is not able to complete the transfer, it will de-assert the TRDY signal and assert the STOP signal having transferred only a portion of the requested data.
When a data block transfer is ended by the target device before completion, the bus master device re-establishes communication with the target device, at a future time, to complete the transfer of the data block. What is typically done in the industry is that the bus master device will immediately begin trying to re-establish data transfer communications with the target device in order to complete the data transfer as quickly as possible. However, immediately retrying a data transfer request can waste PCI cycles if the target device will typically remain busy for a period of time after the data transfer is terminated.
A further problem that arises during DMA data transfers over the PCI.TM. bus is that of erratic data flow. A typical cause for erratic data flow in bus master and target devices is access time for the device's private memory subsystem. Access to a private memory subsystem is typically lengthened due to refresh cycles which coincide with data access cycles, and due to addressing latency when using dynamic memory elements which incur significant address penalties when an access crosses an address page boundary.
The PCI.TM. bus protocol provides a maximum data transfer rate of one longword per 30 ns when operating with a 33 Mhz PCI.TM. bus clock. In order to approach this magnitude of data rate, a bus master and target device combination should be capable of transferring a longword of data to/from the PCI.TM. bus during every PCI.TM. clock cycle. If data is not accessible at this rate due to erratic data flow, PCI.TM. bus bandwidth is wasted which results in a reduction of the overall system performance.
Another problem which impedes the transfer of data over the PCI.TM. bus is the time required to set up the DMA transfer. A chip having DMA capabilities has control structures which keep track of the data to be transferred in each DMA transfer. These structures require significant chip resources and bus bandwidth to initialize and manage the data transfer which detracts from the available time that the chip has to perform the data transfer. Such time delays reduce the DMA data transfer performance on the PCI.TM. bus.
Therefore a data transfer methodology is required which solves these problems and hence increases the data bandwidth of the data bus.